In LDMOS transistors the channel length is typically defined by transport of dopants through ion implantation or diffusion and not by lithographic feature size. A first portion of the channel is based on a traditional MOS transistor with appropriate gate dielectric and doping level. A latter portion of the channel has a much lower doping but has still the same capacitive coupling from the polycrystalline silicon gate. By this, the transconductance of the device is improved, but the potential of the short channel length defined by the doping is not fully utilized since the latter portion of the channel has a parasitic capacitance, which is not desirable.
Typically, the improvement caused by the doping is accepted, whereas the parasitic capacitance of the latter portion of the channel is simply disregarded.
Nevertheless, there have been reports of using a non-uniform oxide thickness for different reasons. By increasing the thickness towards the drift region lower parasitic capacitance can be obtained.